Semiconductor devices and integrated circuits (ICs) are generally contained in semiconductor packages comprising a protective coating or encapsulant to prevent damage during the handling and assembly of the components, during shipping, and when mounting the components on printed circuit boards. For cost reasons, the encapsulant is preferably made of plastic. In a liquid state, the plastic “mold compound” is injected into a mold chamber at an elevated temperature surrounding the device and its interconnections before cooling and curing into a solid plastic. Such packages are commonly referred to as “injection molded”.
Interconnection to the device is performed through a metallic leadframe, generally made of copper, conducting electrical current and heat from the semiconductor device or “die” into the printed circuit board and its surroundings. Connections between the die and the leadframe generally comprise conductive or insulating epoxy to mount the die onto the leadframe's “die pad”, and metallic bond wires, typically gold, copper, or aluminum, to connect the die's surface connections to the leadframe. Alternatively, solder balls, gold bumps, or copper pillars may be used to attach the topside connections of die directly onto the leadframe.
While the metallic leadframe acts as an electrical and thermal conductor in the finished product, during manufacturing the leadframe temporarily holds the device elements together until the plastic hardens. After plastic curing, the packaged die is separated or “singulated” from other packages also formed on the same leadframe by mechanical sawing. The saw cuts through the metal leadframe and in some instances through the hardened plastic too.
In “footed” semiconductor packages, i.e. packages where the metallic leads or “pins” protrude beyond the plastic and terminate in feet, the leads are then bent using mechanical forming to set them into their final shape. The finished devices are then packed into tape and reels ready for assembly onto customers' printed circuit boards (PCBs).
One example of a footed package 1 is shown in FIG. 1A, comprising semiconductor die 5, plastic 2, bond wires 6C and 6D, metallic leads 3B, 3C, 3D and metallic die pad 3A. The metallic leads and lead frame comprise elements from a single lead frame 3 separated during manufacturing. Leads 3B, 3C and 3D are thinner than metallic die pad 3A, exiting plastic body 2 at a height above the bottom surface 8 of the die pad 3A (shown also in FIG. 1B) and must be bent down in curved sections 4B, 4C and 4D so that the non-curved portion of metallic leads 3B, 3C and 3D lie flat or “coplanar” on a PCB with the planar bottom surface 8 of metallic die pad 3A. Such a package is sometimes referred to as a “gull-wing” package owing to its shape of its bent leads.
Such footed packages are manufactured in a large variety of sizes and pin configurations ranging from 3 leads used for packaging transistors and simple ICs such as bipolar junction transistors, power MOSFETs and shunt voltage regulators, to dozens of leads used for packaging integrated circuits (ICs). To date, many billions of products have been manufactured using injection-molded footed plastic packages. Common packages include small transistor packages like the SC70 and SOT23 packages, small outline packages such as the SOP-8, SOP-16 or SOP-24, and for higher pin counts, the footed quad flat pack or LQFP. The LQFP, which can have 64 or more leads per package, apportions its leads in even amounts on each of its four edges while SOT and SOP packages have leads positioned on only two sides.
To accommodate the lead bending process, minimum package heights for the SOP and LQFP typically exceed 1.8 mm. Some packages, including the small outline transistor package such as the SOT23-3, SOT23-5, SOT23-6 and the SOT223, the small chip package such as the SC70, the TSOP-8 thin small outline package, and the TSSOP-8 thin super small outline package, have been engineered for lower profiles, as thin as 1 mm. Below a 1 mm thickness, it becomes difficult to manufacture any of these packages. Even for taller package heights, maintaining good lead coplanarity during lead bending is a constant concern in the volume manufacturing of gull-wing packages.
Accurate forming of leads to tight specifications and tolerances is problematic. Customers consider deformed leads as quality failures, demanding a formal corrective action response and a committed improvement schedule. In extreme cases, manufacturing outside of specified tolerances can result in manufacturing interruptions, triggering financial penalties, vendor disqualifications and even litigation. Poor control of lead bending in manufacturing is not the only limitation of these packages. Because package height is a major consideration in IC packages, the leadframe is limited in thickness, typically to 200 μm or less, and it therefore exhibits relatively poor power dissipation capability because of the inability to effectively spread heat from a die into the printed circuit board or heat sink.
Power packages like the DPAK or D2PAK construction shown in FIG. 1A use much thicker metal, specifically 500 μm, 2.5 times that of integrated circuit packages. As such, IC packages and power packages have diverged in their manufacturing methods over time with ICs becoming more “high tech,” requiring sophisticated manufacturing and applicable for use only in expensive reflow printed circuit board (PCB) assembly lines. Power packages in contrast rely on older “low tech” factories and processes, and are generally board mounted in legacy PCB factories using “wave solder” techniques. For the same PCB area, wave solder based factories can manufacture a substantially lower cost—one half to one quarter the cost of reflow assembly factories.
Because of their antiquity, the minimum dimensions and tolerances in power packages tend to be much larger than modern IC packages. Again referring to FIG. 1A, the pin pitch between leads 3C, 3B and 3D is 1.5 mm. In contrast, ICs today commonly employ 0.4 mm center-to-center pin spacing. A cross-sectional view of package 1 taken in a cut line along and through lead 3D is shown in FIG. 1B comprising die pad 3A used as both an electrical and thermal conductor, lead 3D not connected to die pad 3A, semiconductor die 5, conductive bond wire 6D, and molded plastic 2. Die pad 3A includes an upper surface 18 and lower surface 8 and is encased on four sides by molded plastic 2. Die pad 3A also extends laterally beyond molded plastic 2 by a distance 16 and includes an exposed surface along upper surface 18 not encased by molded plastic 2.
Conductive lead 3D exits molded plastic 2 parallel to lower surface 8 at a height above lower surface 8 but below the top surface of molded plastic 2. Conductive lead 3D is mechanically bent into bent portion 4D so that the end of conductive lead 3D sits atop and is coplanar with lower surface 8. A specific metallic portion of the surface of die 5 called the bonding pad is bonded to conductive lead 3D by conductive bond wire 6D, enabling electrical connection from a printed circuit board to the bonding pad. Bond wire 6D may comprise gold, aluminum, or copper. The bonding pad may constitute a specific dedicated metallized area, e.g. a gate pad, or in the case of large power devices may comprise a large array of metal that sits atop a large array of active transistors.
For example, in a vertical power MOSFET or insulated gate bipolar transistor (IGBT), typically the large area top metal of die 5 electrically connects to the source of the device, a smaller bonding pad connects to its gate or input, and the backside of die 5 electrically connects the drain or output of the device directly to die pad 3A through die attach 35, a thin electrically conductive layer of glue or solder. In manufacturing, bond wire 6D must not sag and touch die pad 3A or the device will become electrically shorted. In very high current devices, bond wire 6D may be replaced by a copper “clip”, a bent piece of metal contacting the large area conductor's surface on die 5 and the conductive lead 3D. In some package designs, the vertical position of conductive lead 3D is not coplanar with the upper surface 18 of die pad 3A.
During manufacturing, since bending occurs after plastic molding, bent portion 4D much be spaced by lateral distance 17 from molded plastic 2 or permanent damage to molded plastic 2 such as cracking, chipping, and delamination between conductive lead 3D and molded plastic 2 may result. Such damage can result in yield loss during visual inspection, and uncaught, can result in reliability failures. Another source of manufacturing defect can occur if bent portion 4D is bent too much or too little so that the bottom portion of conductive lead 3D is not coplanar with the planar bottom surface 8 of die pad 3A.
A similar, but slightly different cross section shown in FIG. 1C represents the cross section taken as a cut line along and through conductive lead 3B. In this case, lead 3B is physically and electrically connected to die pad 3A. Like conductive lead 3C and others, conductive lead 3B cannot be bent with bent portion 4B being any closer to molded plastic 2 than a minimum lateral distance 17, or molded plastic 2 may be damaged.
An underside plan view of package 1, i.e. the bottom of the package coplanar to planar bottom surface 8, is illustrated in FIG. 1D, where the exposed bottom side of die pad 3A is surrounded on three sides by molded plastic 2 except for the metallic portion 16 or “tab” extending beyond the plastic. The portion of the leads 3C, 3B and 3D not in planar bottom surface 8 are illustrated as dashed lines, including corresponding bent portions 4C, 4B and 4D.
The first step of manufacturing is illustrated FIG. 2A, showing die pad 3A in two different cross sections, the top figure representing the cross section through and along conductive lead 3B, and the lower illustration representing the cross section through and along conductive lead 3C. Fabrication commences with a solid piece of copper, optionally plated with a thin coating of tin used to improve solderability, which is masked by a protective layer, i.e. mask 30, typically comprising patterned photoresist or an organic material not susceptible to acid. Mask 30 may be applied uniformly and then selectively removed, e.g. using optical exposure to define the areas to be removed, or alternatively may be applied selectively through a stencil mask.
After application and patterning, patterned mask 30 is baked to harden the material. The copper piece is then etched in an acid, e.g. hydrochloric acid comprising HCL:FeCl3:H2O in a 4:1:5 mixture, nitric acid comprising HNO3:H2O2 in a 1:20 mixture, or ammonia comprising NH3:H2O2 in a 4:1 mixture. If the copper is pre-plated with a thin layer of tin (Sn), then the tin must first be removed by etching using hydrofluoric acid comprising HF:HCL in a 1:1 mixture, HF:HNO3 in a 1:1 mixture, or HF:H2O in a 1:1 mixture. A more thorough list of common wet chemical metal etches can be found in semiconductor process textbooks or online at http://www.cleanroom.byu.edufwet_etch.phtml. The tin and copper may be etched on one side or by immersion in an acid bath. In the case of immersion etching, to prevent unwanted etching and thinning of the leadframe the metal leadframe's backside must be coated by another protective layer. For clarity's sake, this backside protection is not shown in the illustrations but is well known by those skilled in the art of semiconductor packaging.
Returning to FIG. 2A, after etching, the copper forms an L-shape with a thick portion comprising die pad 3A and a thin “diving board” projection designated 3Z. Patterned mask 30 is then removed before processing continues. At this step the cross section shown is identical for both illustrations representing the two aforementioned cross sections. In FIG. 2B, a patterned mask 31 is applied and etching is repeated to etch through a portion of the diving board projection 3Z. In the upper illustration, the diving board projection 3Z is protected, resulting in lead 3B, while in the lower illustration the diving board projection 3Z is separated by etching from die pad 3A resulting in independent lead 3D and gap 32. Lead 3D is held in place by connection to the surrounding lead frame not shown. After etching, protective mask 31 is removed.
Next, as shown in FIG. 2C, semiconductor die 5 is attached to die pad 3A using thin die attach layer 35 comprising either solder or conductive epoxy. In the lower cross section of FIG. 2D, one or more bond wires 6D are bonded atop semiconductor die 5 connecting it to lead 3D. In the upper cross section, no bond wires are required because die attach 35 electrically connects the backside of die 5 to die pad 3A and hence to lead 3B. After wire bonding, plastic molding using transfer molding techniques are then used, as depicted in FIG. 2E, to form molded plastic 2 encapsulating semiconductor die 5, bond wire 6D and other bond wires (not shown), and portions of die pad 3A, leads 3B, 3D and other leads (not shown). In semiconductors, transfer molding is preferred over injection molding because it gives a superior mold with less flash to remove.
In FIG. 2F leads 3B and 3D are bent by a mechanical “forming” tool, producing bent portions 4B and 4D in their corresponding leads so that the bottom of the leads lies coplanar with the bottom surface 8 of leadframe 3A. Finally the leads are clipped, disconnecting leads 3B and 3D from leadframe 3G. This cutting operation is known as “singulation” because one leadframe containing many packaged dice is cut or broken into separate, “singular” packaged dice. In the bending operation, the mechanical forming tool firmly holds and supports the leads in space 17 to prevent stress from the operation from cracking molded plastic 2. The length of space 17 is determined by the dimension specified by the manufacturer of the mechanical forming tool and cannot be reduced below the minimum specified dimension without risking damage to the package during manufacturing. It is apparent from FIG. 2F that space 17 and bent portions 4B and 4D represent “wasted” PCB area because they do not contain active semiconductor dice and they do represent a useful PCB area, either. Because of its poor area efficiency, this package technology is therefore incompatible with space-sensitive applications such as smartphones and mobile personal electronics.
FIG. 3A illustrates the plan view of a printed circuit board 100 located beneath the conductive traces used for mounting footed package 1 onto the PCB, i.e. the PCB landing pads. The landing pads contain four areas for soldering the components of package 1 onto the PCB: conductor 41C for soldering to the end of lead 3C, conductor 41B for soldering to the end of lead 3B, conductor 41D for soldering to the end of lead 3D, and the fourth area, the large landing pad comprising conductor 41A, for soldering to the bottom of the package's die pad 3A. In the case of leads 3C, 3B and 3D, the solder can be applied from above using wave soldering. Through surface tension, the solder will naturally wet onto the lead and onto the PCB conductive trace. Held in position temporarily either mechanically, by glue or by tape, molten solder affixes itself onto the leads and PCB trace and once cooled hardens into a solid, holding the package in place.
The wave-soldering method of applying solder does not work in the large landing pad of conductor 41A used to connect to the package's die pad 3A. (The dashed line labeled “3A” indicates where die pad 3A is to be positioned.) In this case, a thin piece of solder 45, must be manually deposited onto the PCB before package 1 is placed onto the PCB and die pad 3A must then be soldered into place by heating in an oven before wave-soldering is performed. During wave-soldering the die pad 3A may float on the solder and move slightly from its target position, making the soldering process somewhat imprecise. To prevent shorts on the PCB, components cannot be mounted too closely to one another. Dashed line 44 represents a “keep out” zone where no other component can be mounted to avoid electrical shorts. Depending on a PCB manufacturer's design rules, this keep out zone 44 can substantially increase the area needed to mount a component on a PCB and greatly reduce the areal packing density of devices.
FIG. 3B illustrates a cross section of package 1 mounted onto a two layer PCB 100. As shown. PCB 100 comprises a lower conductor layer 43A and 43B, upper conductor layer 41A and 41B and an intervening insulating layer with conductive via 42 located within portions of PCB. As shown, die pad 3A is soldered onto PCB conductor 41B by intervening solder layer 45 placed atop the PCB 100 before the package leads are soldered. Solder layer 45 is generally melted before wave soldering. After wave soldering, solder electrically connects lead 3D to PCB conductor 41A. A characteristic of wave soldering is it connects the sides of lead 3D to PCB conductor 41A through solder 34D, but that no intervening solder is present between lead 3D and PCB conductor 41A.
So in “low tech” PCB manufacturing lines, wave soldering is used to solder all the components except for the large die pads of power packages, which instead require solder or solder paste to be manually placed or dispensed prior to power component placement. Such a manual method of placing solder is slow and expensive, and therefore cost effective when used for only for few components. As shown, solder 34A from the wave soldering process also creeps up onto the side of die pad 3A. While such a solder joint may be adequate for carrying the rated current of a power component, it does not insure a low thermal resistance between die pad 3A and PCB conductor 41B, 42, and 43B. As such, the use of solder paste 45 in wave solder manufacturing remains unavoidable when power components are mixed with other ICs.
An alternative PCB assembly method, known as reflow manufacturing, involves printing solder paste across the entire printed circuit board before mounting the components, but this process, while very precise, is slow and therefore expensive, especially since high cost reflow ovens are required to melt the solder in a controlled manner to avoid movement of the components from floating during soldering. Although mandatory in smartphone, tablet, notebook, and mobile device manufacturing, reflow PCB assembly is rarely used in larger low-cost consumer devices such as TVs, automotive electronics, consumer products, white goods, or in power supply modules.
One common device packaged in a package 1 shown in FIG. 1A is a vertical power MOSFET comprising three electrical terminals, the MOSFET drain electrically connected from the backside of semiconductor die 5, a gate input wire-bonded with a single wire to a gate pad on the top side of the die, and a source requiring multiple source bond wires bonded to large topside metal covering most of the die's surface. The electrical equivalent of a power MOSFET mounted in the aforementioned package is illustrated in FIG. 3C where the gate of power MOSFET 47 is connected to conductive lead 3C, the source of power MOSFET 47 is connected by bond wires 6D to conductive lead 3D, and the backside drain is connected to die pad 3A as well as to conductive lead 3B. The high current path includes parasitic inductance 49A of magnitude LS in the source connection resulting from the source bond wires, and parasitic inductance 49B of magnitude LD in the drain connection resulting from the package leadframe construction.
In operation, source inductance 49A is a greater concern for several reasons. Firstly, conductive lead 3B can be used to monitor the true drain voltage of MOSFET 47 bypassing the high current flowing through die pad 3A and its parasitic inductance 49B. Source inductance 49A comprising bond wire inductance can be substantial, even where LS>LD. Unlike in the drain connection, which has both the backside die pad 3A and conductive lead 3B as connections, a separate sense lead to measure the true source voltage of MOSFET 47 is not available in package 1. In circuit operation, however, stray source inductance is problematic and much worse than drain inductance.
Specifically in switching a power MOSFET off, any change in the drain current can cause the source voltage on MOSFET 47 to oscillate. As the source voltage oscillates, the gate-to source voltage may rise and fall above the MOSFET's threshold voltage, turning it on and off multiple times and increasing the switching loss accordingly. In high-speed switching, a separate conductor connecting to the true source of power MOSFET 47 and bypassing source inductance 49A would be advantageous. Unfortunately, such a conductive lead is not possible in present day DPAK and D2PAK packages because conductive lead 3B is used for mechanical support during assembly and necessarily must be tied to die pad 3A.
The role of conductive lead 3B is illustrated in FIG. 4A, where die pad 3A attaches to leadframe bar 38 through lead 3B. So while conductive leads 3C and 3D need not attach to die pad 3A, conductive lead 3B must attach to die pad 3A, otherwise nothing would hold it in place during manufacturing, i.e. during the die mounting, wire bonding, molding, or during trim and forming steps.
The leadframe also illustrates that each die is encapsulated by discrete pieces of molded plastic 2, with multiple cavities required specifically matched to the leadframe. The corresponding mold tool to form the plastic body encapsulating the die and its bond wires is illustrated in FIG. 4B comprising a top mold tool 37B and a lower plate 37A, when pushed together forms a mold cavity for molded plastic 2. Each and any change in the leadframe pitch or package size change requires a new mold to be fabricated, an expensive component requiring involving precision-machined steel molds.
Conventional mold machines are large, typically weighing 200 tons, or 250 tons for the mold press and the mold base. Including the mold cavity tool, the combined cost of such a system is typically of $150,000 USD for the first package type plus another $100,000 USD for each additional package. Newer generation mold machines are even more expensive, even double in price. Moreover, whenever the leadframe and cavity width or pitch of a package is changed, other equipment such as trim and form machines must be modified adding an additional expense of $70,000 USD or more to accommodate the new package form factor.
As such, each mold cavity is a fixed width unique to a specific package and leadframe for example DPAK or D2PAK are different. Using the standardized lead pitch, only three conductive leads per package are possible without modifying the mold tool and mold cavity width. But since, as described previously, the die pad is necessarily tied to the center conductive lead, these standardized packages can only accommodate up to three separate electrical connections.
Devices that utilize packages limited to three electrical connections can be broadly categorized into three types, namely two-terminal devices, three-terminal vertical devices, and three-terminal lateral devices. FIG. 5A illustrates a simplified cross-sectional example of a two terminal vertical device comprising a topside metal 23A, bulk semiconductor material 20 and overlying epitaxial layer 21, backside contact 22 sitting atop a die pad (not shown) on planar surface 18. Topside metallization 23A contacts bond wire 6D in a bonding pad area defined by an opening in passivation layer 48. Beneath passivation layer 48, an oxide or glass layer 25 protects the surface of the device from contamination. In operation, current flows vertically from topside metal 23A through epitaxial layer 21 and substrate 20 to backside metal contact 22. The junctions present in epitaxial layer 21, i.e. the construction of the semiconductor device, are not important in the context of understanding the direction of the main current flow and are not shown. Two-terminal devices generally comprise semiconductor diodes and rectifiers although protection devices and voltage clamps are also examples.
FIG. 5B illustrates a simplified cross-sectional illustration of a three-terminal vertical power device, which as in the previous illustration comprises topside metal 23A, bulk semiconductor material 20 and overlying epitaxial layer 21, along with backside contact 22 sitting atop a die pad (not shown) on planar surface 18. As shown, topside metallization 23A is contacted by bond wire 6D in a bonding pad area defined by an opening in passivation layer 48, representing the high-current connection of the device with the main current flowing vertically from metal 23A to backside metal contact 22.
In areas other than top metal 23A, an oxide layer 25 protects the surface of the device from contamination. In one area, a metal layer 23B sitting atop a portion of oxide layer 25 that is not covered by passivation 48 comprises a second bonding pad contacted by bond wire 6C. This type of connection is used for a gate or input to a device. Examples of three-terminal vertical power devices include, power bipolar transistors, vertical power MOSFETs, insulated gate bipolar transistors (IGBTs), and thyristors. The cross section shown does not include junctions present in each specific device type's construction except to illustrate the main current flow is vertical and a second bonding pad is included as a gate input.
FIG. 6 illustrates the same package can also be used for three-terminal lateral devices whereby the electrical contact to epitaxial layer 45 and substrate 44 by bond wire 6B and top side metal 23B does not constitute the high current path in the device. Instead, the main current in the device flows laterally between bond pad 23D, contacted by bond wire 6D, and bond pad 23A, contacted by bond wire 6A. Because the main current flows through two bond wires instead of only one bond wire, as in the case of vertical devices, the packaging of lateral devices unavoidably suffers from higher parasitic package. i.e. wire, resistance. Another difference is that in the case of a lateral device, the main current of the device does not flow vertically, so a backside contact of substrate 44 and the associated backside metal is not required.
In summary, today's high volume power packages had seen little advancement since their inception decades ago. Factory lines for DPAK and D2PAK packages are inflexible, requiring large expenses to accommodate multiple package types. The packages intrinsically are limited to a maximum of three electrical terminals, limiting their applicability to only a few device types. The package's center conductive lead is necessarily shorted to the die pad, further limiting layout options for a semiconductor device. The packages are area-inefficient, with large “keep out” tones and long conductive leads necessary to facilitate lead bending without damaging the molded plastic encapsulant. The large package dimensions and long bond wires contribute to undesirable parasitic resistance and inductance. Lead bending is imprecise, making it difficult to insure good co-planarity of the leads with the bottom of the exposed die pad and adversely impacting PCB assembly yield. And with all the forgoing limitations, the possibility to enhance today's power package design and manufacturing capability to accommodate low profile or multi-lead packages remains problematic both technically and economically.
What is needed is a new generation of power package capable of offering low-profile low-inductance and multi-lead capability with superior co-planarity in a flexible, versatile, and cost effective manufacturing line.